The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a multilayer interconnection structure and fabrication process thereof.
In recent semiconductor integrated circuit devices, a vast number of semiconductor elements are formed on a common substrate, and a multilayer connection structure is used for interconnecting these semiconductor elements.
In multilayer interconnection structure, interlayer insulation films embedded with interconnection patterns constituting an interconnection layer are laminated, and a lower interconnection layer is connected to an upper interconnection layer by way of a via-contact formed in the interlayer insulation film.
In the ultrafine and ultra fast-speed semiconductor devices of these days, a low-dielectric film (so-called low-K film) is used for the interlayer insulation film together with low-resistance Cu pattern used for the interconnection pattern, for reducing the problem of signal delay caused in the multilayer interconnection structure.
In such multilayer interconnection structure in which a Cu interconnection pattern is embedded in a low-K interlayer insulation film, a so-called damascene process or dual damascene process is used in view of the difficulty of patterning a Cu layer by way of dry etching process. In damascene process or dual damascene process, interconnection trenches or via-holes are formed in the interlayer insulation film in advance, and a Cu layer is formed so as to fill the interconnection trenches or via-holes thus formed. Further, excessive Cu layer on the interlayer insulation film is removed by a chemical mechanical polishing (CMP) process.
Thereby, in order to avoid the problem of short circuit or the like, caused when the Cu interconnection pattern has made a direct contact with the interlayer insulation film by the Cu atoms invading into the interlayer insulation film by diffusion, it is practiced in the art to cover the sidewall surfaces and bottom surface of the interconnection trenches or via-holes, on which the Cu interconnection patterns are to be formed, by a conductive diffusion barrier, or so-called barrier metal film, of a refractory metal such as Ta or W or conductive nitride of such a refractory metal element, and to deposit the Cu layer on such a barrier metal film.
On the other hand, with recent ultrafine and ultra fast-speed semiconductor devices of the generation of 45 nm node or later, significant demagnification is in progress with regard to the size of the interconnection trenches and via-holes formed in the interlayer insulation film in correspondence to device miniaturization, and thus, there is a need of decreasing the film thickness of the barrier films formed on such a minute interconnection trenches or via-holes when to maintain the desired decrease of interconnection resistance while using such a conventional barrier metal films, which has a large specific resistance. On the other hand, there is a need that the barrier metal film covers the sidewall surfaces and the bottom surface of the interconnection trenches or via-holes continuously.
Conventionally, use of MOCVD (metal organic CVD) process or ALD (atomic layer deposition) process has been studied as the technology capable of forming extremely thin barrier metal films continuously on such highly miniaturized interconnection trenches or via-holes.
However, such MOCVD process or ALD process generally uses metal organic vapor source, and because of this, the barrier metal film of refractory metal or refractory metal nitride formed with such a process suffers from the problem of poor film quality, in spite of its capability of forming a thin and uniform film. For example, there arises a serious problem of adhesion between the barrier metal film and the interlayer insulation film particularly when a low-dielectric interlayer insulation film of low density, such as inorganic low-K film of SiOCH film or SiC film or organic insulation film, is used.
Meanwhile, US20050218519A describes the technology of covering the interconnection trenches or via-holes in the interlayer insulation film directly with a Cu—Mn alloy layer and forming a manganese silicon oxide layer of the composition of MnSixOy as a diffusion barrier film at the interface between the Cu—Mn alloy layer and the interlayer insulation film with the thickness of 2-3 nm, by inducing a self-forming reaction between Mn in the Cu—Mn alloy layer and Si and oxygen in the interlayer insulation film.
FIGS. 1A-1D show the method of forming a Cu interconnection structure according to US20050218519A.
Referring to FIG. 1A, there is embedded a Cu interconnection pattern 11A in an interlayer insulation film 11 via an ordinary barrier metal film 11B of Ta, TaN, or the like, wherein there are formed interlayer insulation films 13 and 15 over the interlayer insulation film 11 via an etching stopper film 12 of SiC or SiN such that an etching stopper film 14 of SiC or SiN is interposed between the interlayer insulation films 13 and 15. Further, in the state of FIG. 1A, there is formed an interconnection trench 15A in the interlayer insulation film 15 so as to expose the interlayer insulation film 13 at the bottom part thereof, and a via hole 13A is formed in the interlayer insulation film 13 so as to expose the Cu interconnection pattern 11A.
Next, in the step of FIG. 1B, a Cu—Mn alloy layer 16 is formed on the structure of FIG. 1A so as to cover the sidewall surfaces and bottom surface of the interconnection trench 15A and the sidewall surface and the bottom surface of the via hole 13A continuously and directly, wherein the Cu—Mn alloy layer 16 is formed with a thickness of several nanometers by an evaporation deposition process of sputtering process. Further, electroplating process is conducted in the step of FIG. 1C while using the Cu—Mn alloy layer as a seed layer, and as a result, a Cu layer 17 is formed on the interlayer insulation film 15 so as to film the interconnection trench 15A and the via-hole 13A.
Further, in the step of FIG. 1D, the structure of FIG. 1C is annealed in an oxygen gas ambient at the temperature of 400° C., for example. With this, the Mn atoms in the Cu—Mn layer 16 are caused to react with the Si atoms and the oxygen atoms of the interlayer insulation films 13 and 15 exposed at the sidewall surfaces and bottom surfaces of the interconnection trench 15A and the via-hole 13A, and as a result, there is formed a diffusion barrier film 18M of the composition of MnSixOy at the surface of the interconnection trench 15A and the via-hole 13A.
It should be noted that the reaction of FIG. 2D forming the MnSixOy diffusion barrier film 18M is a self-forming reaction or self-organizing reaction characterized by self-limiting phenomenon, and the growth of the MnSixOy layer stops spontaneously, although it depends upon the nature of the underlying film, when the thickness thereof has reached 2-3 nm. Thus, according to such a process, it becomes possible to form an extremely thin diffusion barrier film with extremely uniform film thickness and with reliability.
It should be noted that the etching stopper film 14 is formed of SiC or SiN, while an SiC film or SiN film also contains a small amount of oxygen, and formation of the extremely thin MnSixOy diffusion barrier film 18M takes place also on the exposed surface of the etching stopper film similarly. On the other hand, the Cu interconnection pattern 11A is subjected to a process of removal of native oxide film prior to the step of FIG. 1B by a reverse sputtering process, or the like, and is thus free from oxygen. Thus, there occurs no formation of the diffusion barrier film 18M at the interface between the Cu interconnection pattern 11A and the Cu layer 17. Thus, a direct and good contact is attained between the Cu interconnection pattern 11A and the Cu layer 17.
In the thermal annealing process of FIG. 1D, the Mn atoms contained in the Cu—Mn alloy layer 16 but not contributing to the formation of the MnSixOy layer cause diffusion into the Cu layer 17 and form a Mn oxide layer 18 having a composition represented as MnxOy by causing reaction with oxygen in the ambient when reached the surface of the Cu layer 17. This is because that Mn has a larger ionization tendency over Cu. Thus, in the step of FIG. 1D, not only the barrier metal film 18M is formed, but there also occurs precipitation of Mn atoms in the Cu layer 17 on the surface of the Cu layer 17 in the form of the Mn oxide layer 18, and as a result, there is caused decrease of Mn concentration in the Cu layer 17, leading to reducing of specific resistance of the Cu layer 17.
Further, in the step of FIG. 1E, the excessive Cu layer 17 on the interlayer insulation film 15 is removed together with the foregoing Mn oxide layer 18 by a CMP process, and with this, a Cu pattern 18 filling the via-hole 13A and the interconnection trench 15A is formed together with the uniform MnSixOy diffusion barrier film 18M of the thickness of 2-3 nm.
Meanwhile, the inventor of the present invention has noted, in the investigation constituting the foundation of the present invention, about the possibility that there may be formed stable Mn oxide film on the surface of the Cu—Mn alloy layer 16 in the initial phase of thermal annealing process at the time of transition from the step of FIG. 1C to the thermal annealing process of FIG. 1D and that the transition to the structure of FIG. 1D may be hampered as a result of formation of such a stable Mn oxide film.
FIGS. 2A and 2B are SIMS profile diagrams showing the distribution of Cu, Mn and O atoms in the interlayer insulation film 15, the Cu—Mn alloy layer 18M and the Cu layer 17 along the cross-section A-A′ in the state of FIG. 1D. It should be noted that the SIMS profile of FIGS. 2A and 2B was discovered for the first time by the inventor of the present invention in the investigation that constitutes the foundation of the present invention, wherein FIG. 2A shows the state before annealing while FIG. 2B shows the state after annealing at 350° C. for 30 minutes.
Referring to FIGS. 2A and 2B, it can be seen that there appears a spike of Mn and oxygen at the interface between the Cu—Mn alloy layer 18M and the interlayer insulation film 15 in correspondence to the expected thin MnSiOx layer or MnxOy layer, while there is also observed a spike of Mn and oxygen at the surface of the Cu—Mn alloy layer 18, and hence at the interface to the Cu layer 17, indicating formation of a Mn oxide layer also in this part.
Such a Mn oxide layer functions to block the excessive Mn atoms in the Cu—Mn alloy layer 18M from causing diffusion to the surface of the Cu layer 17, and thus, it becomes difficult to decrease the specific resistance in the Cu pattern 17A of FIG. 1E when there occurs formation of such an Mn oxide layer.